This project involves the development of analytic models that can be used to evaluate the performance of computer systems. During the past year, the work on modeling and analyzing computer systems using the graph theoretic model called Timed Place-Transition (P-T) Nets was continued. This included the development of new methods for determining net invariants and new models for demonstrating the dynamics of computer systems. Detailed models of computer bus control techniques and the operation of a commercial array processor were constructed. These models were analyzed using a method that was developed for evaluating computer system performance with Timed P-T Net models. CSL continued to develop a state variable P-T Net model of the interconnection of two or more microprocessors that provides a framework for determining the avoidance of deadlock and the maintenance of throughput in multiple microprocessor systems. In FY84, Timed P-T Nets will be used to develop more analytic tools for evaluating computer system performance.